The field-effect transistor has undergone radical changes over the years, but the same basic principle is still powering our chips. That won’t change in the foreseeable future.
Back in the day, when the world was a simpler place, transistors were planar. Source, channel and drain were differently doped regions of silicon positioned next to each other. Slap a dielectric layer and a gate on top, and you had yourself a metal-oxide-semiconductor field-effect transistor (MOSFET).
With only minor tweaks, the MOSFET served as the semiconductor industry’s workhorse for decades. It allowed itself to be shrunk so willingly that Moore’s Law was understood to be about the increasing component density of integrated circuits, even though it was very clear that there was a bit more to chip complexity than that.
In the late 00s, however, the trusty steed was showing signs of old age. As the MOSFET’s channel region became shorter and shorter, it became easier and easier for charge to sneak across. The result is a transistor that’s never completely off, wasting power and unnecessarily generating heat.
And so the MOSFET started on an evolutionary journey to plug the leaks. 2011 saw the introduction of the FinFET architecture, in which the channel is raised to a 3D fin structure with the gate draped over it on three sides. Compared to its predecessor, however, the FinFET will run out of steam much more quickly: soon, leading-edge chipmakers will move to gate-all-around (GAA) designs. With gates enveloping channels completely, what room for improvement is left? Are we approaching the end of the road for the good old FET? No, there’s still some life in it left, says Imec.
Beyond the 5nm node, electrostatic control in a FinFET starts to become problematic. Additionally, FinFETs don’t provide as much flexibility as one would like when it comes to balancing the transistor’s speed, power consumption and cost.
Channel width is an important variable in making this trade-off. In planar devices, adjusting the geometry is simple. Unfortunately, the dimensions of fins aren’t nearly as flexible, and channel dimensions are more or less dictated by multiples of whole fins. This is especially restricting when a mix of wide and narrow fins (for high-performance and low-power computing, respectively) are desired in a single IC.
And so FinFETs will give way to GAA structures. Demonstrated in research as early as 1990, a GAA transistor is like a sliced-up FinFET fin flipped on its side. With each of the horizontal sheets completely wrapped by the gate, channel control is obviously superior. The channel’s cross-section is quantized like in the FinFET, but it’s less painful to stack sheets on top of each other than put fins next to each other: the former consumes less precious wafer area.
The GAA will be even more short-lived than the FinFET. The most promising device architecture to succeed it is the forksheet FET, according to Imec. The forksheet is a natural extension of the GAA nanosheet design but allows for a much tighter spacing of nFET and pFET devices. In FinFET architectures, two dummy fins are typically required between n and p transistors, consuming a lot of extra space. In the forksheet, the n- and pMOS devices are placed side-by-side in a single structure, separated by an isolating dielectric ‘wall.’
After the forksheet, Imec is anticipating the complementary FET. The CFET features n- and p-type GAAs stacked on top of each other. Two transistors occupying the space of one isn’t the main benefit of this technology, however: simplification of transistor terminal access is. Chip components are getting so small that it’s hard to connect them all reliably.
After so many ‘makeovers,’ the original MOSFET may have become unrecognizable, but the basic principle powering our chips still hasn’t changed. Nor will it be traded in for a completely different paradigm any time soon. “In recent years, several people have claimed that traditional CMOS scaling has already come to an end. But with many innovations in the pipeline, we’re convinced that we can continue CMOS scaling for at least the next ten years,” said Naoto Horiguchi, director of Imec’s logic CMOS scaling program.