UT spin-off Qbaylogic intends to position its Clash language as the third language for programming FPGAs, in addition to and above VHDL and Verilog. Demcon’s involvement will enable the company to grow further and develop new products.
Last month, Enschede-based technology developer and manufacturer Demcon acquired a share in Qbaylogic. This spin-off from the University of Twente has created a new hardware description language for FPGAs, called Clash, as an alternative or supplement to the low-level languages VHDL and (System) Verilog. The company was taken on by Demcon’s incubator program in 2016, enabling it to support clients in the development of hardware. A successful project for Demcon confirmed the potential of Clash. Demcon’s financial involvement will enable Qbaylogic to grow further and develop new products, such as tools to accelerate working with the language.
Clash is intended for functionally programming FPGAs at a higher level of abstraction, describing the structure or architecture of an application in terms of the desired functionality. It automatically translates the functional design into the actual hardware programming in VHDL or (System) Verilog. Thus, for example, computational operations can be programmed in parallel, while the classical languages work sequentially, and therefore only extract half the maximum performance from an FPGA. With Clash, according to Qbaylogic, you can squeeze the most out of it, which makes the resulting architecture cheaper, faster and more energy-efficient. In addition, a program can be tested more quickly and easily than with, for example, VHDL.
Qbaylogic was founded in 2016 by Jan Kuper and Christiaan Baaij. Kuper had been computer science lecturer at the UT for thirty years. Baaij’s PhD was about the development of Clash, which Kuper had already started in 2007. “The entire world programs in C, C++, Java and Matlab, but if you want to grasp the real essence of computer hardware, you need to switch to a functional hardware description language. That’s why we developed Clash,” Baaij explains. In search of a place to grow organically without external investments, Qbaylogic ended up at Demcon’s incubator program, which offers starting companies accommodation and support with personnel and legal aspects, as well as support with engineering and production.
An initial joint project with Demcon went well, says Joost Kauffman, senior mechatronic systems engineer at Demcon Optomechatronic Systems. “The power of Qbaylogic lies in their toolbox, which is open source and therefore doesn’t involve high licensing costs, and in the fact that they have experienced people who can support us. I expect we’ll have to call on them more often for applications in precision instruments and production machines, including such things as wafer tracking throughout a production process. This needs to take place at high frequency to keep the wafers stable. Then you automatically end up with FPGAs.”
The first partnership involved Demcon and TNO’s development of a wavefront sensor for satellite communications, contracted by the European Space Agency (ESA). This sensor needs to control a deformable mirror to compensate for atmospheric disturbances. Because of the high data speeds, the algorithm for processing all sensor data was programmed using Clash in an FPGA. Demcon called on Qbaylogic for this.
The FPGAs are now working well in the satellite communication system, states Kauffman. “With their approach, Qbaylogic has shown that they can program an application in the hardware faster than when using the traditional approach from mainstream programming languages and that you have more control over the result. You don’t need to worry about errors in the implementation, as the compiler removes these. Moreover, for the required 5 kHz data frequency, the performance couldn’t be achieved with a normal PC. An FPGA does, however, achieve that speed. In addition, the code generated by Clash is extremely efficient, which means you can sometimes use a cheaper FPGA than for code produced in the traditional way. With an FPGA you can, for instance, also time to the nanosecond when data move from A to B or when a certain process is completed. This is important for time-critical processes.”
Qbaylogic is currently working on a few long-term projects for international clients and is receiving more and more requests for project support. And it won’t end there as the company is also working on the development of tools to support the design process, for instance, to enable efficiency testing at an early stage when the hardware is being developed. That’s hardly possible with the methods currently used in practice. Its formal character means that Clash lends itself well to mathematical analysis methods, such as dataflow models. “This will be an important improvement to standard design methods as, with these, to end up with a design that’s efficient enough, you’re largely dependent on trial and error,” explains Baaij.
Kuper adds: “One of our international clients, an extremely large company, is interested in developing such tools. This matches our ambition to expand Clash to become a powerful and flexible development environment for computer hardware. Demcon’s involvement certainly contributes to this.”