Intel “challenges” ASML and others to make bigger high-NA masks

Intel is pushing bigger mask sizes for high-NA EUV lithography and perhaps even low-NA EUV, CEO Pat Gelsinger told the More than Moore blog. “I’m challenging both ASML and my mask-making team to get me to bigger mask sizes so we can get the field size back, and maybe even bigger mask sizes to get even more economics out of EUV overall.”

Mask size and field size, ie the wafer area being exposed in a single exposure step, are connected. The industry standard EUV field and mask sizes are 26 by 33 millimeters and 6 by 6 inches, respectively. To make high-NA work, ASML and Zeiss opted to double the magnification in one direction, resulting in a half-sized field of 26 by 16.5 millimeters. ASML has beefed up the wafer stages to make up for the loss in throughput, but printing larger die sizes with half-sized fields still faces constraints, since images will have to be ‘stitched’ together to create full-sized chips. Going back to the industry standard mask size might also increase throughput.