Imec tips forksheet transistors for sub-2nm CMOS

Imec has come up with a successor to the gate-all-around transistor. At the 2021 Symposia on VLSI Technology and Circuits (VLSI 2021), the Leuven-based research institute demonstrated for the first time fully functional integrated forksheet FETs. “Our electrical characterization results confirm that the forksheet is the most promising device architecture to extend the logic and SRAM scaling roadmaps beyond 2nm, leveraging the nanosheet integration in a non-disruptive way,” commented Naoto Horiguchi, Director CMOS Device Technology at Imec.

As dimensions of transistors shrink, the proximity between the drain and the source lessens the gate electrode’s ability to control the flow of current in the channel. That’s why leading-edge chipmakers in the early 2010s moved to the FinFET architecture, in which the channel is raised to a 3D fin structure with a gate draped over it on three sides. Soon, they’ll start to envelop gates completely, hence the name gate-all-around (GAA) transistors.

As the journey to higher logic density continues, a tighter spacing between nFET and pFET devices will be required. However, for both FinFET and nanosheet devices, process limitations pose a limit to how close these n and p devices can be brought together. In the forksheet transistor, a dielectric wall in between the n- and pMOS devices is introduced, which physically isolates the n-gate trench from the p-gate trench, allowing a much tighter n-to-p spacing than what’s possible with either FinFET or GAA devices.