News

How ASML is planning to continue the shrink

Paul van Gerven
Leestijd: 5 minuten

ASML’s senior vice president technology Jos Benschop recently revealed how the EUV ecosystem centered around his company’s lithography scanners will continue to shrink chip structures for the decade to come.

Going from i-line bulbs in the mid-80s to EUV light sources today, the resolution required to pattern the world’s leading-edge chips has gone down by two orders of magnitude. For a while now, ASML has been saying that this historic trend can continue for at least another decade. But other than putting high-NA EUV lithography on the roadmap, it hasn’t gone into much detail on how this feat will be accomplished. Speaking at the SPIE Advanced Lithography online conference recently, ASML’s senior vice president technology Jos Benschop lifted the curtain.

The issue that his audience probably was most eager to hear about is stochastics. Indeed, Benschop himself referred to it as “the elephant in the room.” Stochastic errors, which are random variations in patterning, have been plaguing EUV lithography right from the start. It has been a hotly debated subject, particularly at specialist forums such as the SPIE AL conference.

This article is exclusively available to premium members of Bits&Chips. Already a premium member? Please log in. Not yet a premium member? Become one and enjoy all the benefits.

Login

Related content