Chip shrinking in the era of system scaling

Paul van Gerven
Leestijd: 3 minuten

Improving semiconductor technology may require a more eclectic approach these days, but shrinking chip structures remains a staple in the industry’s scaling efforts.

“Over the past 15 years, our industry has achieved about 2x energy-efficient performance improvement per 2 years. System performance and energy efficiency will continue to advance at this historical rate,” TSMC chair Mark Liu predicted in his keynote lecture at the 2021 ISSCC. As he was saying the words, the slide on display showed the historical trend being extrapolated to 2040. Almost two more decades for this alternative version of Moore’s Law – that’s quite the statement.

Energy-efficient performance (EEP) is the number of operations a chip performs per second divided by the energy expended per operation. This metric has been proposed to replace raw computing power as a measure of chip performance progress, which stalled around 2006, when Dennard scaling broke down.

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